Cornell University
School of Electrical and Computer Engineering
ECE 5745 Complex Digital ASIC Design
Spring 2023
Prof. Christopher Batten
407 Phillips Hall • Tuesday and Thursday • 1:00–2:15pm
home | syllabus | schedule | readings | handouts | resources
ASIC Resources
RISC-V Resources
- K. Asanovic and D. Patterson. Instruction Sets Should Be Free: The Case for RISC-V UC Berkeley Technical Report No. UCB/EECS-2014-146, August 6, 2014. [ pdf ]
- A. Waterman, Y. Lee, D. Patterson, K. Asanovic. The RISC-V Instruction Set Manual, Volume I: User-Level ISA. Version 2.1. May 31, 2016. [ pdf ]
- A. Waterman, Y. Lee, R. Avizienis, D. Patterson, K. Asanovic. The RISC-V Instruction Set Manual, Volume II: Privileged Architecture. Version 1.9. July 8, 2016. [ pdf ]
- D. Kanter. RISC-V Offers Simple, Modular ISA. Microprocessor Report, The Linley Group, March 28, 2016. [ pdf ]
- RISC-V Reference Card, RISC-V Foundation, 2015. [ pdf ]
- RISC-V Foundation Website
Verilog Coding Resources
- S. Palnitkar. Verilog HDL: A Guide to Digital Design and Synthesis, 2nd edition. Prentice Hall, 2003. [ amazon ]
- S. Sutherland, S. Davidmann, and P. Flake. SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling, 2nd edition. Spring, 2006. [ amazon ]
- C. Spear and G. Tumbush. SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, 3rd edition. Spring, 2012. [ library | amazon | ch1/pdf ]
- S. Sutherland. The IEEE Verilog 1364-2001 Standard: What's New, and Why You Need It, Int'l HDL Conference and Exhibition, 2000. [ pdf ]
- C.E. Cummings. New Verilog-2001 Techniques for Creating Parameterized Models, Int'l HDL Conference and Exhibition, 2002. [ link | pdf ]
- S. Sutherland. Verilog HDL Quick Reference Guide (Verilog-2001), Sutherland HDL, 2001. [ pdf ]
- C.E. Cummings. Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! Synopsys Users Group, San Jose, 2000. [ link | pdf ]
- D. Mills and C.E. Cummings. RTL Coding Styles That Yeild Simulation and Synthesis Mismatches, Snyopsys Users Group, San Jose, 1999. [ link | pdf ]
- S. Sutherland. I'm Still in Love With My X! Design and Verification Conference (DVCon), 2013. [ link | pdf ]
- M. Turpin. The Dangers of Living with an X (bugs hidden in your Verilog), ARM Ltd., 2003. [ pdf ]
Verilog Standards
- Verilog IEEE Standard 1364-1995
- Verilog IEEE Standard 1364-2001
- SystemVerilog 3.1a Language Reference Manual
Python Coding Resources
- A.B. Downey. Think Python: How to Think Like a Computer Scientist, version 2.0.13. O'Reilly, 2014. [ amazon | publisher | pdf ]
- Code Academy Site for Python. [ link ]
Latency-Insensitive Interfaces
- C. Fletcher. EECS150: Interfaces: "FIFO" (a.k.a Ready/Valid). UC Berkeley, 2009. [ pdf ]
- G. Gibeling. GateLib: FIFO Interface. UC Berkeley, 2010. [ pdf ]