Miscellaneous Handouts

• GitHub Username Signup
• Lab Group Signup
• Course Syllabus
• Next Steps after First Lecture
• Project Ideas
• Verilog RTL Usage Rules
• Tiny RISC-V Instruction Set Specification
• Project Report Assessment Rubric

Lecture Handouts

• Course Overview (notes)
• Topic 1: Hardware Description Languages
• Topic 2: CMOS Devices (notes)
• Topic 3: CMOS Circuits (notes)
• Topic 4: Full-Custom Design Methodology (notes)
• Topic 5: Automated Design Methodologies (notes)
• Topic 6: Closing the Gap Between ASIC and Custom (notes)
• Topic 7: Packaging, Power Distribution, Clocking, and I/O
• Topic 8: Testing and Verification
• Topic 9: CMOS Combinational Logic (notes)
• Topic 10: CMOS Sequential State (notes)
• Topic 11: CMOS Interconnect (notes, video)
• Topic 12: Synthesis Algorithms (notes)
• Topic 13: Physical Design Automation Algorithms (notes)

Section Handouts

• Section 1: ASIC Tool Front-End (github)
• Section 2: ASIC Tool Back-End (github)
• Section 3: ASIC Automated Flow (github)
• Section 4: TinyRV2 Accelerators (github)
• Section 5: SRAM Generators (github)
• Section 7: OpenLANE Open-Source Flow from C2S2 (github)

Lab Handouts

• Lab Assignment Logistics
• Lab 1: Pipelined Integer Multiplier (rubric)
• Lab 2: Sorting Accelerator (rubric, results)

Tutorial Handouts

Tutorials 0–3 are from the prerequiste course (ECE 4750 Computer Architecture). We will be using the exact same infrastructure in this course, so they are still applicable.

• Tutorial 0: Remote Access to ecelinux
• Tutorial 1: Linux Development Environment
• Tutorial 2: Git Distributed Version Control System (github)
• Tutorial 3: Verilog Hardware Description Language (github)
• Tutorial 4: Synopsys/Cadence ASIC Tools (github)
• Tutorial 10: SPICE Simulation (github)

Midterm Preparation

• Midterm Example Appendix
• Practice Problem 1 (solutions)
• Practice Problem 2 (solutions)