Reading Assignments

The required textbook for the course is "Digital Design and Computer Architecture, RISC-V Edition," by D. M. Harris and S. L. Harris (Morgan Kaufmann, 2021). There are three different editions of this book for three different instruction set architectures: MIPS, ARM, RISC-V. It is critical that students use the RISC-V edition. All students will have access to the textbook online through Canvas via the Cornell Academic Materials Program.

Students are expected to complete all of the assigned reading according to the schedule below, although there is some flexibility. Some students may prefer to complete the readings before the corresponding lecture, while others may prefer to complete the readings after the corresponding lecture. Either strategy is acceptable.

If a section of the book is on this list, then students are expected to understand the material in that section. If a section of the book is NOT on this list, then students are NOT expected to understand the material in that section. Students are always expected to understand the material presented in lecture.

Course Overview

• Chapter 1. From Zero to One
  • 1.1. The Game Plan
  • 1.2. The Art of Managing Complexity

Topic 1: Digital Circuits

• Chapter 1. From Zero to One
  • 1.7. CMOS Transistors
    • include semiconductors, diodes, capacitors, transistors
    • include CMOS NOT gate, other CMOS logic gates
    • exclude transmission gates, pseudo-nMOS logic
    • exclude power consumption
  • 1.9. Summary and a Look Ahead

Topic 2: Combinational Logic Gates

• Chapter 1. From Zero to One
  • 1.3. The Digital Abstraction
  • 1.5. Logic Gates
  • 1.6. Beneath the Digital Abstraction
• Chapter 2. Combinational Logic Design
  • 2.1. Introduction
  • 2.9. Timing

Topic 3: Boolean Algebra

• Chapter 2. Combinational Logic Design
  • 2.2. Boolean Equations
  • 2.3. Boolean Algebra
  • 2.4. From Logic to Gates
  • 2.5. Multilevel Combinational Logic
  • 2.6. X's and Z's
  • 2.7. Karnaugh Maps

Topic 4: Combinational Building Blocks

• Chapter 2. Combinational Logic Design
  • 2.8. Combinational Building Blocks
  • 2.10. Summary
• Chapter 5. Digital Building Blocks
  • 5.1. Introduction
  • 5.2. Arithmetic Circuits
  • exclude prefix adders, division
  • exclude subtractor, ALU for now

Topic 5: Number Systems

• Chapter 1. From Zero to One
  • 1.4. Number Systems
• Chapter 5. Digital Building Blocks
  • 5.2. Arithmetic Circuits
  • include subtractor, ALU
  • 5.3. Number Systems

Topic 6: Sequential Logic Gates

• Chapter 3. Sequential Logic Design
  • 3.1. Introduction
  • 3.2. Latches and Flip-Flops
    • exclude transistor-level latch and flip-flop designs
  • 3.3. Synchronous Logic Design
  • 3.5. Timing of Sequential Logic
    • include clock skew
    • exclude derivation of resolution time

Topic 7: Finite State Machines

• Chapter 3. Sequential Logic Design
  • 3.4. Finite State Machines

Topic 8: Sequential Building Blocks

• Chapter 3. Sequential Logic Design
  • 3.6. Parallelism
• Chapter 5. Digital Building Blocks
  • 5.4. Sequential Building Blocks
    • exclude scan chains
  • 5.5. Memory Arrays
  • 5.6. Logic Arrays
    • exclude array implementations
  • 5.7. Summary

Topic 9: Instruction Set Architecture

• Chapter 6. Architecture
  • 6.1. Introduction
  • 6.2. Assembly Language
  • 6.3. Programming
    • exclude switch/case statements
    • exclude function calls for now
    • exclude additional arguments and local variables for now
  • 6.4. Machine Language
  • 6.7. Evolution of the RISC-V Architecture
  • 6.8. Another Perspective: x86 Architecture
  • 6.9. Summary
• Chapter 7. Microarchitecture
  • 7.2. Performance Analysis

Topic 10: Single-Cycle Processor

• Chapter 7. Microarchitecture
  • 7.1. Introduction
  • 7.3. Single-Cycle Processor
    • microarchitecture presented in lecture is different from textbook

Topic 11: Multi-Cycle Processor

• Chapter 7. Microarchitecture
  • 7.4. Multi-Cycle Processor
    • microarchitecture presented in lecture is different from textbook

Topic 12: Pipelined Processor

• Chapter 7. Microarchitecture
  • 7.5. Pipelined Processor
    • microarchitecture presented in lecture is different from textbook
  • 7.9. Summary

Topic 13: Assembly Programming

• Chapter 6. Architecture
  • 6.3. Programming
    • include function calls
    • include additional arguments and local variables
  • 6.5. Compiling, Assembling, and Loading

Topic 14: Caches

• Chapter 8. Memory Systems
  • 8.1. Introduction
  • 8.2. Memory System Performance Analysis
  • 8.3. Caches