Miscellaneous Handouts

• Course Syllabus
• Next Steps after First Lecture
• TinyRV1 Instruction Set Manual

Lecture Handouts

• Course Overview (NVIDIA Blackwell video,results from activity)
• T01: Digital Circuits (old version, problems)
• T02: Combinational Logic Gates (problems)
• T03: Boolean Equations (problems)
• T04: Combinational Building Blocks (problems)
• T05: Number Systems (problems)
• T06: Sequential Logic Gates (problems)
• T07: Finite State Machines (example, problems)
• T08: Sequential Building Blocks (problems)
• T09: Instruction Set Architecture (extra)
• T10: Single-Cycle Processors
• T11: Multi-Cycle Processors (states)
• T12: Pipelined Processors
• T13: Cache Concepts

Quiz Handouts

• Quiz 1: Collaboration Policy (solution)
• Quiz 2: Switch-Level Modeling (solution)
• Quiz 3: Gate-Level Timing (solution)
• Quiz 4: Karnaugh Maps (solution)
• Quiz 5: Sequential Logic Gates (solution)
• Quiz 6: Sequential Gate-Level Timing (solution)
• Quiz 7: Sequential Arithmetic (solution)
• Quiz 8: Single-Cycle Processors (solution)
• Quiz 9: Multi-Cycle Processors (solution)
• Quiz 10: Pipelined Processors (solution)

Section Handouts

• Section 1: Linux Development Environment (github)
• Section 2: Verilog Combinational Gate-Level Design (github)
• Section 3: Verilog Testing (github)
• Section 4: Lab 2 Head Start (github)
• Section 5: Verilog Combinational RTL Desgn (github)
• Section 6: Lab 3 Head Start (github)
• Section 7: Verilog Memory Arrays (github)
• Section 8: Pipelined Processors (solutions)

Lab Handouts

• FPGA Development Primer
• Lab 1 (Parts A & B): Five-Bit Numeric Display – Implementation and Verification
• Lab 1 (Parts C & D): Five-Bit Numeric Display – FPGA Analysis/Prototype and Report
• Lab 2 (Parts A & B): Two-Function Calculator – Implementation and Verification
• Lab 2 (Parts C & D): Two-Function Calculator – FPGA Analysis/Prototype and Report
• Lab 3 (Parts A & B): Music Player – Implementation and Verification
• Lab 3 (Parts C & D): Music Player – FPGA Analysis/Prototye and Report
• Lab 3 (Optional): Music Player – Custom Songs
• Lab 4 (Parts A, B, & C): TinyRV1 Processor – Implementation and Verification
• Lab 4 (Part D): TinyRV1 Processor – FPGA Analysis/Prototype (worksheet)

Tutorial Handouts

• Tutorial 0: ECE Linux Server Remote Access
• Tutorial 1: Linux Development Environment
• Tutorial 2: Git Distributed Version Control System (github)